Compartir
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications (en Inglés)
Robert K. Brayton
(Autor)
·
Patrick C. McGeer
(Autor)
·
Springer
· Tapa Blanda
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications (en Inglés) - McGeer, Patrick C. ; Brayton, Robert K.
$ 172.87
$ 265.96
Ahorras: $ 93.08
Elige la lista en la que quieres agregar tu producto o crea una nueva lista
✓ Producto agregado correctamente a la lista de deseos.
Ir a Mis Listas
Origen: Estados Unidos
(Costos de importación incluídos en el precio)
Se enviará desde nuestra bodega entre el
Lunes 15 de Julio y el
Miércoles 24 de Julio.
Lo recibirás en cualquier lugar de Ecuador entre 1 y 3 días hábiles luego del envío.
Reseña del libro "Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications (en Inglés)"
This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under- estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu- racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo- ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit.
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
Todos los libros de nuestro catálogo son Originales.
El libro está escrito en Inglés.
La encuadernación de esta edición es Tapa Blanda.
✓ Producto agregado correctamente al carro, Ir a Pagar.
